This invention relates generally to metallization systems and methods and more particularly to metallization systems and methods suitable for use with very large scale integrated (VLSI) circuits. More particularly, the invention relates to metallization systems having increased electromigration (EM) resistance.
As is known in the art, electromigration (EM) in on-chip electrical interconnects is one of the wearout mechanisms which limit the lifetime of integrated circuits. On-chip interconnects are typically made of highly-conductive, polycrystalline metal films, such as aluminum, copper, or their alloys. In such films, electromigration typically proceeds along the network of grain boundaries. EM failures, in the form of voids or hillocks, usually occur at certain grain-boundary intersections, called "triple points", where flux divergence exists, i.e., the flux of metallic atoms entering the intersection is different from the flux of atoms leaving this intersection. However, EM failure is even more likely to occur at the end of a metal conductor where it is attached to an interlevel contact or via. At the same time, as discussed in a paper entitled, "Electromigration in thin aluminum films on titanium nitride" by I. A. Blech, published in the Journal of Applied Physics, Vol. 47, No. 4, April 1976, pages 1203-1208, EM voids and hillocks cannot develop in metal lines or conductors which are shorter than a certain "critical length". The "critical length" effect was observed in A1/W/A1 via chains as reported in "Evidence of the electromigration short-length effect in aluminum-based metallurgy with tungsten diffusion barriers" by Ronald G. Filippi et al, Proceedings of MRS Symposium, Vol. 309, 1993 pages 141-148 and in a paper entitled "Permitted Electromigration of Tungsten-Plug vias in Chain for Test Structure with Short Inter-Plug Distance", by T. Aoki et al., published in Proceedings of VMIC Conference, 1994 beginning at page 266. The critical length effect in all-aluminum lines with polycrystalline segments has been reported in a paper entitled "Two Electromigration Failure Modes in Polycrystalline Aluminum Interconnects", by E. Atakov, J. J. Clement and B. Miner, published in the Proceeding of the IRPS, 1994, beginning at page 213. At typical operating conditions of silicon integrated circuits, the critical length is expected to be at least 100 um, as discussed in the above reference papers.
Prolongation of the lifetime of a contact to the silicon substrate by forming a gap in one layer of a multilayered metal line within the critical distance from the contact, and filling the gap with a refractory metal has been reported in a paper entitled "An Increase of the Electromigration Reliability of Ohmic Contacts by Enhancing Backflow Effects", by Wei Zhang, et al., Proceedings of the IRPS, 1995, beginning at page 365. As described in the Zhang et al. paper, a 4000 .ANG. thick Al-1% Si electrically conductive film is deposited over a 4700 .ANG. thick dielectric layer and through a contact opening formed in a region of a dielectric layer to make electrical contact with an electric device formed in a semiconductor body, as shown in FIG. 1 of the paper. The Al-1% Si layer is patterned to form a stripe which is attached to the contact and has a gap at a critical distance, L.sub.c, from the contact. A 3200 .ANG. thick trilevel metallization layer made of 100 .ANG. thick Ti, 3000 .ANG. thick W, 100 .ANG. thick Ti is deposited over the substrate, covering the Al-1% Si stripe and filling the gap. Next a 4000 .ANG. thick Al-1% Si layer is deposited over the surface. Because the gap presumably has a depth of the thickness of the first Al-1% Si layer (i.e., a depth of 4000 .ANG.), it appears that the resulting metal surface is non-planar.
The two top metallization layers are patterned to form a stacked stripe coincident with the first Al-1% Si stripe. The first stripe itself is non-planar, making it difficult to perform photolithography to align the stacked stripe. Because of non-planarity, the process described by Wei Zhang, et al. does not ensure the dimension control which is required to fabricate devices with submicron feature size. Particularly, it cannot easily be used to fabricate the conductors in high-performance, state-of-the-art Very Large Integrated Circuits (VLSI).
One of the requirements for metal interconnects in such circuits is that the equidistant conductors be spaced at submicron distance. Very tight dimensional control is required for the fabrication process to ensure such small distance without causing unintended electrical shorts between the conductors.
Also, the structure proposed by Wei Zhang et al., does not provide complete blocking of electromigration, because aluminum can migrate away from the contact in the top conducting layer of Al-1% Si. On the other hand, even though the gap can somewhat prolong the life of the nearby contact, the gap itself creates a flux divergence and is a likely site for an EM failure.
Interconnect structures with a plurality of high electrically conductive, electromigration-prone segments separated by very short, electromigration-resistant refractory metal segments were proposed in U.S. Pat. No. 5,439,731, entitled Interconnect Structures Containing Blocking Segments to Minimize Stress Migration and Electromigration Damage, by Li et al., issued on Aug. 8, 1995.
However, Li et al., propose that the high electrically conductive segments be formed first, and the gaps between the segments be filled with EM-resistant metal afterwards. Another photolithography/metal etch step is required to form the intended interconnect structure. This method has the same disadvantage as the method proposed by Wei Zhang, et al.
Conductors in high-performance VLSI are required to have as low electrical resistance as possible. The EM-resistant refractory metals are known to have a lower electrical conductivity than Al, Au, Cu, etc. For this reason, it is critical that the method which is used to form the interconnect structures allow for making the EM-resistant segments as short as possible.
Also for the purpose of reducing the overall resistance of segmented conductors, it is desirable that the high electrically conductive segments be as long as possible, without compromising the conductor reliability. Li et al., propose that the high electrically conductive segments be as short as 5 to 20 microns. However, it was shown that the high electrically conductive segments are immune to electromigration if they are no longer than the critical length, L.sub.c. As discussed by I. A. Blech, L.sub.c is inversely proportional to the electrical current density in the conductor, and L.sub.c depends on the physical characteristics of the conductor and the overlying dielectric. L.sub.c can be determined using special experimental techniques. As shown by R. G. Filippi et al., and T. Aoki et al., L.sub.c can be as long as 100 um or even longer for state-of-the-art VLSI conductors at typical VLSI operating currents.